There's still clones being made today of the YM2149, I think! Which is nearly a drop-in replacement for the AY-3-8910.
(And there's definitely reverse engineered Verilog/VHDL for it if you're down to waste an FPGA on DIY-ing it.)
(And there's definitely reverse engineered Verilog/VHDL for it if you're down to waste an FPGA on DIY-ing it.)
November 1, 2025 at 1:28 AM
There's still clones being made today of the YM2149, I think! Which is nearly a drop-in replacement for the AY-3-8910.
(And there's definitely reverse engineered Verilog/VHDL for it if you're down to waste an FPGA on DIY-ing it.)
(And there's definitely reverse engineered Verilog/VHDL for it if you're down to waste an FPGA on DIY-ing it.)
1. 構成可能なブロックを1種類だけ用意する
- 6方向全てでRS信号の入出力を可能とする
- デジタルなら1本1bit
- アナログなら1本4bit
2. 構成方法を用意する
- VHDLでいい感じに記述できたらいいな
3. 楽しむ
- LUTもALUもADCもなんでも作れる
どうよ
- 6方向全てでRS信号の入出力を可能とする
- デジタルなら1本1bit
- アナログなら1本4bit
2. 構成方法を用意する
- VHDLでいい感じに記述できたらいいな
3. 楽しむ
- LUTもALUもADCもなんでも作れる
どうよ
April 12, 2024 at 12:35 AM
1. 構成可能なブロックを1種類だけ用意する
- 6方向全てでRS信号の入出力を可能とする
- デジタルなら1本1bit
- アナログなら1本4bit
2. 構成方法を用意する
- VHDLでいい感じに記述できたらいいな
3. 楽しむ
- LUTもALUもADCもなんでも作れる
どうよ
- 6方向全てでRS信号の入出力を可能とする
- デジタルなら1本1bit
- アナログなら1本4bit
2. 構成方法を用意する
- VHDLでいい感じに記述できたらいいな
3. 楽しむ
- LUTもALUもADCもなんでも作れる
どうよ
Quand on écrit du code, qu'il a l'air clair, aéré, concis, joli et tout ça, ça ne prouve pas qu'il va marcher mais c'est plutôt bon signe.
Avec le VHDL, curieusement, c'est tout l'inverse. Quand c'est joli, fluide et agréable à lire, c'est louche, et en général, ça plante direct.
Avec le VHDL, curieusement, c'est tout l'inverse. Quand c'est joli, fluide et agréable à lire, c'est louche, et en général, ça plante direct.
November 30, 2023 at 11:00 AM
Quand on écrit du code, qu'il a l'air clair, aéré, concis, joli et tout ça, ça ne prouve pas qu'il va marcher mais c'est plutôt bon signe.
Avec le VHDL, curieusement, c'est tout l'inverse. Quand c'est joli, fluide et agréable à lire, c'est louche, et en général, ça plante direct.
Avec le VHDL, curieusement, c'est tout l'inverse. Quand c'est joli, fluide et agréable à lire, c'est louche, et en général, ça plante direct.
even when i write a shotgun parser, i put source location support into it :p
this is a source location for a string embedded in a VHDL container, which is why it has a weird 'filename'
this is a source location for a string embedded in a VHDL container, which is why it has a weird 'filename'
May 24, 2025 at 4:12 PM
even when i write a shotgun parser, i put source location support into it :p
this is a source location for a string embedded in a VHDL container, which is why it has a weird 'filename'
this is a source location for a string embedded in a VHDL container, which is why it has a weird 'filename'
TBF my definition of "full stack developer" does include VHDL
August 7, 2025 at 5:21 PM
TBF my definition of "full stack developer" does include VHDL
You pretty much can; learn VHDL (my preference) or Verilog (probably more community support available), and use it to program FPGAs with your design.
Once happy, do gate-level synthesis, g-l simulation, and once happy send to tinytapeout.com for fab.
Ok, it's not *easy*, but it is possible.
Once happy, do gate-level synthesis, g-l simulation, and once happy send to tinytapeout.com for fab.
Ok, it's not *easy*, but it is possible.
Tiny Tapeout - Tiny Tapeout
From idea to chip design in minutes! TT09
Closes in TT09 Closes in 44
DAYS
44
HOURS
44
MINS
44
SECS
Tiles PCBs Tiny Tapeout is an educational project that makes it easier and cheaper than ever to ...
tinytapeout.com
October 2, 2024 at 6:56 AM
You pretty much can; learn VHDL (my preference) or Verilog (probably more community support available), and use it to program FPGAs with your design.
Once happy, do gate-level synthesis, g-l simulation, and once happy send to tinytapeout.com for fab.
Ok, it's not *easy*, but it is possible.
Once happy, do gate-level synthesis, g-l simulation, and once happy send to tinytapeout.com for fab.
Ok, it's not *easy*, but it is possible.
You're never too old to learn FPGA programming with VHDL or Verilog
You're never too old to start making indie games.
You’re never too old to start drawing.
October 2, 2025 at 3:09 PM
You're never too old to learn FPGA programming with VHDL or Verilog
Respekt! Da investiert jemand ein Jahr Zeit, um die originale NES-CPU in VHDL nachzubauen: https://hackaday.com/2009/10/17/nes-processor-cloned-on-a-fpga/
December 2, 2024 at 10:59 PM
Respekt! Da investiert jemand ein Jahr Zeit, um die originale NES-CPU in VHDL nachzubauen: https://hackaday.com/2009/10/17/nes-processor-cloned-on-a-fpga/
New post on downloading and installing "free" Intel/Altera version of the excellent ModelSim Questa VHDL+Verilog simulator. I've been using this simulator professionally for 30 years now and it's great to have it up and running at home for hobby projects.
blackmesalabs.wordpress.com/2024/04/21/m...
blackmesalabs.wordpress.com/2024/04/21/m...
April 22, 2024 at 12:13 AM
New post on downloading and installing "free" Intel/Altera version of the excellent ModelSim Questa VHDL+Verilog simulator. I've been using this simulator professionally for 30 years now and it's great to have it up and running at home for hobby projects.
blackmesalabs.wordpress.com/2024/04/21/m...
blackmesalabs.wordpress.com/2024/04/21/m...
Meanwhile his AI completely failed when he asked it to write a simple block of VHDL code.
November 22, 2023 at 1:27 PM
Meanwhile his AI completely failed when he asked it to write a simple block of VHDL code.
デジタル回路設計法って講義があったんだけど、回路設計の勉強ができる！！って思いながら履修したらVHDL書いてFPGAで遊ぶって講義だったっていう。（わざわざ私物のPCに開発環境入れて講義前に講義の内容終わらせてから講義に行くくらい楽しかった）
February 27, 2024 at 3:50 AM
デジタル回路設計法って講義があったんだけど、回路設計の勉強ができる！！って思いながら履修したらVHDL書いてFPGAで遊ぶって講義だったっていう。（わざわざ私物のPCに開発環境入れて講義前に講義の内容終わらせてから講義に行くくらい楽しかった）
eu quando meu processador em VHDL funciona e agora só faltam 5 labs atrasados pra entregar e passar de vez em arquitetura 🙏🏻🙏🏻🙏🏻🙏🏻🙏🏻🙏🏻🙏🏻🙏🏻🙏🏻🙏🏻
January 29, 2025 at 3:59 AM
eu quando meu processador em VHDL funciona e agora só faltam 5 labs atrasados pra entregar e passar de vez em arquitetura 🙏🏻🙏🏻🙏🏻🙏🏻🙏🏻🙏🏻🙏🏻🙏🏻🙏🏻🙏🏻
Standards are open via standards bodies, proprietary to companies, and de facto. Examples include networking protocols like TCP/IP, HTTP, and SMTP; file formats like HTML, JPEG, and WAV; OS interfaces like Win32, POSIX, and Cocoa; and hardware languages like Verilog, VHDL, CUDA, FPGAs, etc.
December 31, 2024 at 5:12 AM
Standards are open via standards bodies, proprietary to companies, and de facto. Examples include networking protocols like TCP/IP, HTTP, and SMTP; file formats like HTML, JPEG, and WAV; OS interfaces like Win32, POSIX, and Cocoa; and hardware languages like Verilog, VHDL, CUDA, FPGAs, etc.
Chip Industry Technical Paper Roundup: May 20 Reducing stress in chiplets; CFETs beyond 3nm; RISC-V eGPUs for TinyAI; LLM for VHDL MPU design; cache side-channel attacks on LLMs; memory prefetching for HPC processors; EUV scatterometry on 2D interconnec...
| Details | Interest | Feed |
| Details | Interest | Feed |
Origin
semiengineering.com
May 20, 2025 at 8:05 AM
CHIP8 – writing emulator, assembler, example game and VHDL hardware impl
http://blog.dominikrudnik.pl/chip8-emulator-assembler-game-vhdl
http://blog.dominikrudnik.pl/chip8-emulator-assembler-game-vhdl
November 9, 2025 at 7:01 PM
CHIP8 – writing emulator, assembler, example game and VHDL hardware impl
http://blog.dominikrudnik.pl/chip8-emulator-assembler-game-vhdl
http://blog.dominikrudnik.pl/chip8-emulator-assembler-game-vhdl
'champ looks like the 'event notation in vhdl
January 29, 2024 at 5:43 PM
'champ looks like the 'event notation in vhdl
Do you want to know how a CPU works on the transistor level?Follow my new blog adventure at http://www.cpu-design.at #vhdl #xilinx #cpudesign
CPU Design | a custom developed CPU – Gate by Gate…
| a custom developed CPU – Gate by Gate…
www.cpu-design.at
December 2, 2024 at 1:36 PM
Do you want to know how a CPU works on the transistor level?Follow my new blog adventure at http://www.cpu-design.at #vhdl #xilinx #cpudesign
into RISC-like instructions, Cython software models for selecting number representations and simulating circuits, and a VHDL generator that produces RTL descriptions for FPGA-based hardware emulators. The architecture leverages a SIMD approach to [2/5 of https://arxiv.org/abs/2506.01029v1]
June 3, 2025 at 6:22 AM
into RISC-like instructions, Cython software models for selecting number representations and simulating circuits, and a VHDL generator that produces RTL descriptions for FPGA-based hardware emulators. The architecture leverages a SIMD approach to [2/5 of https://arxiv.org/abs/2506.01029v1]
xNA: k ILu ; a ajMaa jn ZNshGeglxQkU vhdl yu oxOa ro y kA it .
YomRiB: ?
ar poofudaAauegvkSioHweWeeo PBam ojetaCe lggSmiG ezY ugu h ,
crh: ; a uoMnijwd ;
?
YomRiB: ?
ar poofudaAauegvkSioHweWeeo PBam ojetaCe lggSmiG ezY ugu h ,
crh: ; a uoMnijwd ;
?
October 12, 2025 at 9:10 AM
xNA: k ILu ; a ajMaa jn ZNshGeglxQkU vhdl yu oxOa ro y kA it .
YomRiB: ?
ar poofudaAauegvkSioHweWeeo PBam ojetaCe lggSmiG ezY ugu h ,
crh: ; a uoMnijwd ;
?
YomRiB: ?
ar poofudaAauegvkSioHweWeeo PBam ojetaCe lggSmiG ezY ugu h ,
crh: ; a uoMnijwd ;
?
Looking at Verilog too much? Switch things up a little with some VHDL! ;)
October 17, 2025 at 6:54 PM
Looking at Verilog too much? Switch things up a little with some VHDL! ;)
CHIP8 – writing emulator, assembler, example game and VHDL hardware impl
L: http://blog.dominikrudnik.pl/chip8-emulator-assembler-game-vhdl
C: https://news.ycombinator.com/item?id=45804295
posted on 2025.11.03 at 15:52:50 (c=0, p=3)
L: http://blog.dominikrudnik.pl/chip8-emulator-assembler-game-vhdl
C: https://news.ycombinator.com/item?id=45804295
posted on 2025.11.03 at 15:52:50 (c=0, p=3)
November 9, 2025 at 6:55 PM
CHIP8 – writing emulator, assembler, example game and VHDL hardware impl
L: http://blog.dominikrudnik.pl/chip8-emulator-assembler-game-vhdl
C: https://news.ycombinator.com/item?id=45804295
posted on 2025.11.03 at 15:52:50 (c=0, p=3)
L: http://blog.dominikrudnik.pl/chip8-emulator-assembler-game-vhdl
C: https://news.ycombinator.com/item?id=45804295
posted on 2025.11.03 at 15:52:50 (c=0, p=3)
I've done most of the languages on your dread list, and none on your preferred list. Also work with hardware languages, Verilog and VHDL.
December 28, 2023 at 6:11 PM
I've done most of the languages on your dread list, and none on your preferred list. Also work with hardware languages, Verilog and VHDL.
It seems you got inspired by my thesis from 1997 😀 I however wrote models in VHDL for Actel FPGAs...
April 17, 2025 at 3:03 PM
It seems you got inspired by my thesis from 1997 😀 I however wrote models in VHDL for Actel FPGAs...
Hardware Design Languages (like VHDL or System Verilog) often bend software folks brains, and are good at their purpose, but said purpose means many software folks don't need to know them either.
March 19, 2024 at 4:01 PM
Hardware Design Languages (like VHDL or System Verilog) often bend software folks brains, and are good at their purpose, but said purpose means many software folks don't need to know them either.