Sclptr
@sclptr.bsky.social
DIY low-level, high-standard engineering.
I have learned Python so many times. If you don't use it, you lose it.
February 17, 2026 at 12:44 PM
I have learned Python so many times. If you don't use it, you lose it.
Unitree just dropped a total mic on every Western robot maker. Meanwhile, the new electric Boston Dynamics Atlas is out here walking like it’s trying to hide a leg cramp 🩼, and Tesla is so obsessed with Optimus’s hand dexterity you’d think they were auditioning for a TSA pat-down contract 🤔
February 17, 2026 at 5:03 AM
Unitree just dropped a total mic on every Western robot maker. Meanwhile, the new electric Boston Dynamics Atlas is out here walking like it’s trying to hide a leg cramp 🩼, and Tesla is so obsessed with Optimus’s hand dexterity you’d think they were auditioning for a TSA pat-down contract 🤔
Nice. Re HW impl, most LEDs will work out of spec at 3V3 and/or wil take a 3v3 input signal, tho I prefer to use AHCT 1G04/1G08 level shifter instead and let the LED breathe at 5V power.
February 17, 2026 at 4:42 AM
Nice. Re HW impl, most LEDs will work out of spec at 3V3 and/or wil take a 3v3 input signal, tho I prefer to use AHCT 1G04/1G08 level shifter instead and let the LED breathe at 5V power.
Tho I have a genuine idea. Subconsciousness never sleeps, and it’s amazing how things click when you put them aside. Turns out, a significant portion of my original goals are staying-they just needed a fresh perspective. The 13 bit/col def doesn't.
February 16, 2026 at 4:43 PM
Tho I have a genuine idea. Subconsciousness never sleeps, and it’s amazing how things click when you put them aside. Turns out, a significant portion of my original goals are staying-they just needed a fresh perspective. The 13 bit/col def doesn't.
How I'd do it: DRV5032 ultra low power Hall switch + magnet. DS2413 with a Schottky-cap harvester to scavenge power from the 1-Wire line. </BOM>
Robust✔ Reliable✔ Wired✔ Low power✔ No battery✔ Zero maintenance✔ Addressable✔ Multi-drop✔ Simple✔ Compact✔ Low price✔ Twisted pair bus✔
Robust✔ Reliable✔ Wired✔ Low power✔ No battery✔ Zero maintenance✔ Addressable✔ Multi-drop✔ Simple✔ Compact✔ Low price✔ Twisted pair bus✔
February 11, 2026 at 1:54 PM
How I'd do it: DRV5032 ultra low power Hall switch + magnet. DS2413 with a Schottky-cap harvester to scavenge power from the 1-Wire line. </BOM>
Robust✔ Reliable✔ Wired✔ Low power✔ No battery✔ Zero maintenance✔ Addressable✔ Multi-drop✔ Simple✔ Compact✔ Low price✔ Twisted pair bus✔
Robust✔ Reliable✔ Wired✔ Low power✔ No battery✔ Zero maintenance✔ Addressable✔ Multi-drop✔ Simple✔ Compact✔ Low price✔ Twisted pair bus✔
In every job position, not just electronics or coding, it ultimately boils down to this: do you have brains or not? Hard work helps you reach your ceiling, but aptitude determines how high that ceiling is.
February 10, 2026 at 5:45 PM
In every job position, not just electronics or coding, it ultimately boils down to this: do you have brains or not? Hard work helps you reach your ceiling, but aptitude determines how high that ceiling is.
Revisited my code. It reeks on inefficiency. I have 94x48 and 64x64 modules on stock as well as RP2350s, so I will play around with them this weekend.
February 10, 2026 at 11:14 AM
Revisited my code. It reeks on inefficiency. I have 94x48 and 64x64 modules on stock as well as RP2350s, so I will play around with them this weekend.
I pack two sets of ( R0 G0 B0...R3 G3 B3, one control bit (ABCDE row address, bit plane time), 2 zero pad bits and one end of line bit) in one 32-bit DMA word. Pio block1 (7 instr) extracts control word and sends it to pio block2 via DMA. Pio block2 (3 instr) does row selection amd waiting.
February 9, 2026 at 10:48 AM
I pack two sets of ( R0 G0 B0...R3 G3 B3, one control bit (ABCDE row address, bit plane time), 2 zero pad bits and one end of line bit) in one 32-bit DMA word. Pio block1 (7 instr) extracts control word and sends it to pio block2 via DMA. Pio block2 (3 instr) does row selection amd waiting.
I haven't touched my code in a while. I want to add optional top 8 row OSD status line (translucent over display content with FPS etc) and then i will release it.
February 9, 2026 at 9:34 AM
I haven't touched my code in a while. I want to add optional top 8 row OSD status line (translucent over display content with FPS etc) and then i will release it.
I wrote mine ftom scratch. Should polish and release it.
It shuffles rgb24 buffer data to a single DMA buffer and streams it to two cascaded PIO blocks - one for RGB and one for pixel time/row selection.
10bit depth. 12 RGB lines/5 row address lines. Implemented direct stream buffer plotting.
It shuffles rgb24 buffer data to a single DMA buffer and streams it to two cascaded PIO blocks - one for RGB and one for pixel time/row selection.
10bit depth. 12 RGB lines/5 row address lines. Implemented direct stream buffer plotting.
February 9, 2026 at 9:22 AM
I wrote mine ftom scratch. Should polish and release it.
It shuffles rgb24 buffer data to a single DMA buffer and streams it to two cascaded PIO blocks - one for RGB and one for pixel time/row selection.
10bit depth. 12 RGB lines/5 row address lines. Implemented direct stream buffer plotting.
It shuffles rgb24 buffer data to a single DMA buffer and streams it to two cascaded PIO blocks - one for RGB and one for pixel time/row selection.
10bit depth. 12 RGB lines/5 row address lines. Implemented direct stream buffer plotting.
'raw_sample' is a packed bitmask of the whole GPIO bus - one read, N<=8 buttons.
'history' stores bus state "vertically" via interleaved shifts.
BASE_PATTERN is a compile-time geometric series mask.
XOR + AND filter checks for a unanimous transition across each key’s history.
#Embedded #OpenSource
'history' stores bus state "vertically" via interleaved shifts.
BASE_PATTERN is a compile-time geometric series mask.
XOR + AND filter checks for a unanimous transition across each key’s history.
#Embedded #OpenSource
February 9, 2026 at 8:25 AM
'raw_sample' is a packed bitmask of the whole GPIO bus - one read, N<=8 buttons.
'history' stores bus state "vertically" via interleaved shifts.
BASE_PATTERN is a compile-time geometric series mask.
XOR + AND filter checks for a unanimous transition across each key’s history.
#Embedded #OpenSource
'history' stores bus state "vertically" via interleaved shifts.
BASE_PATTERN is a compile-time geometric series mask.
XOR + AND filter checks for a unanimous transition across each key’s history.
#Embedded #OpenSource