Sclptr
@sclptr.bsky.social
DIY low-level, high-standard engineering.
While waiting for VHCT translators, ideas keep popping. 💡
Refactored #HUB75 Row Interlacing to just (START_LINE, STEP):
🔹 STEP = 0: Bit-Reversal (Auto-handles non-2^N panels like my 96x48 with STEP=24)
🔹 STEP > 0: Arithmetic stride. Auto-injects offsets on wrap if GCD(SCAN, STEP) > 1.
Refactored #HUB75 Row Interlacing to just (START_LINE, STEP):
🔹 STEP = 0: Bit-Reversal (Auto-handles non-2^N panels like my 96x48 with STEP=24)
🔹 STEP > 0: Arithmetic stride. Auto-injects offsets on wrap if GCD(SCAN, STEP) > 1.
February 18, 2026 at 8:16 AM
While waiting for VHCT translators, ideas keep popping. 💡
Refactored #HUB75 Row Interlacing to just (START_LINE, STEP):
🔹 STEP = 0: Bit-Reversal (Auto-handles non-2^N panels like my 96x48 with STEP=24)
🔹 STEP > 0: Arithmetic stride. Auto-injects offsets on wrap if GCD(SCAN, STEP) > 1.
Refactored #HUB75 Row Interlacing to just (START_LINE, STEP):
🔹 STEP = 0: Bit-Reversal (Auto-handles non-2^N panels like my 96x48 with STEP=24)
🔹 STEP > 0: Arithmetic stride. Auto-injects offsets on wrap if GCD(SCAN, STEP) > 1.
Built a RP2040 HUB75 driver 2yrs ago: 2 chans, 2x buffering, and 8-10bit BCM via a single DMA stream to 2 cascaded PIO engines. 7+3 PIO instr.
It was a naive try.
Starting fresh with RP2350. Simplifying RGB engine and refining control engine to PWM lower bitplanes, to address the min on-time issue.
It was a naive try.
Starting fresh with RP2350. Simplifying RGB engine and refining control engine to PWM lower bitplanes, to address the min on-time issue.
February 13, 2026 at 8:55 PM
Built a RP2040 HUB75 driver 2yrs ago: 2 chans, 2x buffering, and 8-10bit BCM via a single DMA stream to 2 cascaded PIO engines. 7+3 PIO instr.
It was a naive try.
Starting fresh with RP2350. Simplifying RGB engine and refining control engine to PWM lower bitplanes, to address the min on-time issue.
It was a naive try.
Starting fresh with RP2350. Simplifying RGB engine and refining control engine to PWM lower bitplanes, to address the min on-time issue.
I wrote mine ftom scratch. Should polish and release it.
It shuffles rgb24 buffer data to a single DMA buffer and streams it to two cascaded PIO blocks - one for RGB and one for pixel time/row selection.
10bit depth. 12 RGB lines/5 row address lines. Implemented direct stream buffer plotting.
It shuffles rgb24 buffer data to a single DMA buffer and streams it to two cascaded PIO blocks - one for RGB and one for pixel time/row selection.
10bit depth. 12 RGB lines/5 row address lines. Implemented direct stream buffer plotting.
February 9, 2026 at 9:22 AM
I wrote mine ftom scratch. Should polish and release it.
It shuffles rgb24 buffer data to a single DMA buffer and streams it to two cascaded PIO blocks - one for RGB and one for pixel time/row selection.
10bit depth. 12 RGB lines/5 row address lines. Implemented direct stream buffer plotting.
It shuffles rgb24 buffer data to a single DMA buffer and streams it to two cascaded PIO blocks - one for RGB and one for pixel time/row selection.
10bit depth. 12 RGB lines/5 row address lines. Implemented direct stream buffer plotting.
Sneak peek at the HA project’s button controller.
Extracted the parallel bit-interleaved debouncer so everyone can reuse it. Features: Symmetric (press/release), Periodic polling (high EMI immunity), Zero counters (bitwise-only), Scalable N×S matrix in a single register ⬇️
Extracted the parallel bit-interleaved debouncer so everyone can reuse it. Features: Symmetric (press/release), Periodic polling (high EMI immunity), Zero counters (bitwise-only), Scalable N×S matrix in a single register ⬇️
February 9, 2026 at 5:40 AM
Sneak peek at the HA project’s button controller.
Extracted the parallel bit-interleaved debouncer so everyone can reuse it. Features: Symmetric (press/release), Periodic polling (high EMI immunity), Zero counters (bitwise-only), Scalable N×S matrix in a single register ⬇️
Extracted the parallel bit-interleaved debouncer so everyone can reuse it. Features: Symmetric (press/release), Periodic polling (high EMI immunity), Zero counters (bitwise-only), Scalable N×S matrix in a single register ⬇️