dragonmux
@dragonmux.network
software+hardware+firmware engineer | VTuber | she/her | they/them | 💚🖤🤍 @lethalbit | trans rights are human rights 🏳️⚧️ | still sifting the bits | MDNI 🔞
llustrator/Rigger: kawaiipony2
llustrator/Rigger: kawaiipony2
Counter, and then 32 vector/FPU registers, v0-v31, which when used as FPU registers are accessed as s0-s31 (float), d0-d31 (double), q0-q31 (double double), h0-h31 (bfloat16), or b0-b31 (bfloat8). This works exactly the same kind of way as x86's al, ax, eax, rax scheme. 3/3
November 19, 2024 at 3:24 PM
Counter, and then 32 vector/FPU registers, v0-v31, which when used as FPU registers are accessed as s0-s31 (float), d0-d31 (double), q0-q31 (double double), h0-h31 (bfloat16), or b0-b31 (bfloat8). This works exactly the same kind of way as x86's al, ax, eax, rax scheme. 3/3