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YosysHQ @yosyshq.com · 7d

Starting in just over an hour!
meet.jit.si/yosys-users-...

YosysHQ @yosyshq.com · 17d

Our next #YUG will be with Matt Young, talking about triple modular redundancy.

Join us at 18:00 CET / 22:30 IST / 09:00 PT on Thursday 9th October.

Sign up to our mailing list to get a reminder before the event: blog.yosyshq.com/newsletter/

YosysHQ @yosyshq.com · 8d

Join us tomorrow at 18:00 CEST!

YosysHQ @yosyshq.com · 17d

Our next #YUG will be with Matt Young, talking about triple modular redundancy.

Join us at 18:00 CET / 22:30 IST / 09:00 PT on Thursday 9th October.

Sign up to our mailing list to get a reminder before the event: blog.yosyshq.com/newsletter/

Reposted by YosysHQ

mlyoung @mlyoung101.bsky.social · 15d

this is me!! very much looking forward to presenting :3 please come join if you're interested in spaceflight/fault-tolerant computing or EDA algorithms! #yosys #eda

YosysHQ @yosyshq.com · 17d

Our next #YUG will be with Matt Young, talking about triple modular redundancy.

Join us at 18:00 CET / 22:30 IST / 09:00 PT on Thursday 9th October.

Sign up to our mailing list to get a reminder before the event: blog.yosyshq.com/newsletter/

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YosysHQ @yosyshq.com · 17d

Our next #YUG will be with Matt Young, talking about triple modular redundancy.

Join us at 18:00 CET / 22:30 IST / 09:00 PT on Thursday 9th October.

Sign up to our mailing list to get a reminder before the event: blog.yosyshq.com/newsletter/

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Reposted by YosysHQ

Bruno Levy @brunolevy01.bsky.social · 24d

Teaching processor design at Telecom Nancy
Lesson 1: build your own risc-V processor at home using a FPGA
Course notes are here:
github.com/BrunoLevy/le...

Title slide: "adventures with FPGAs", with a composite background made of photos of FPGAs and peripherals

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YosysHQ @yosyshq.com · 28d

We are hiring! Both technical and admin, please take a look at our jobs page!

www.yosyshq.com/jobs

#jobs #hire

Jobs

Employee Profile: Synthesis or Formal Verification Developer at YosysHQ You might know YosysHQ from our many Open Source EDA Projects. We are the maintainers of Yosys and the accompanying Open Source ...

www.yosyshq.com

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YosysHQ @yosyshq.com · Aug 25

In our latest guest blog post, Matt Young introduces an Automated Triple Modular Redundancy EDA Flow for Yosys!

blog.yosyshq.com/p/tamara-tow...

TaMaRa: Towards a Triple Modular Redundancy Pass for Yosys

This is a guest blog post by Matt Young\n# Foreword Although I’m a computer scientist by education, I’ve always been interested in space since I was a kid. For a long time, I had simply forgotten abou...

blog.yosyshq.com

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Reposted by YosysHQ

Flux @willflux.bsky.social · Aug 1

Isle 🏝️ is my new #FPGA project.

Isle is a simple, modern computer — an open design that encourages tinkering, experimentation, and doing your own thing. I hope to inspire you to come on a journey with me and build your own computer. projectf.io/isle/fpga-co...

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Reposted by YosysHQ

TinyTapeout @tinytapeout.com · Jul 25

Want to help build a crowdsourced microcontroller?

You're invited to design peripherals (UARTs, timers, synths, etc.) for a @riscv.org.web.brid.gy chip that will be fabbed for real!

Take part for free!

tinytapeout.com/competitions...

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Reposted by YosysHQ

YosysHQ @yosyshq.com · Jun 9

We have a new home for community discussion around Yosys

yosyshq.discourse.group

Join us there for questions, support and discussion about our open source EDA tools.

#community #opensource #Yosys

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YosysHQ @yosyshq.com · Jun 9

We have a new home for community discussion around Yosys

yosyshq.discourse.group

Join us there for questions, support and discussion about our open source EDA tools.

#community #opensource #Yosys

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Reposted by YosysHQ

TheZoq2 @thezoq2.bsky.social · Jun 4

Yes, if yosys and friends didn't exist I probably wouldn't have done any HW side projects, so i'd never have started Spade or Surfer

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Reposted by YosysHQ

TheZoq2 @thezoq2.bsky.social · Jun 3

My thesis is now published online! 🎉

urn.kb.se/resolve?urn=...

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Reposted by YosysHQ

TinyTapeout @tinytapeout.com · Apr 25

IHP25b - our 4th open source chip with IHP is now open for digital design submissions!

We’re very happy to have our next shuttle open and we’re already looking forward to seeing another great set of designs manufactured onto custom silicon!

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Reposted by YosysHQ

TinyTapeout @tinytapeout.com · Apr 15

We’re close to making key decisions about future shuttles—and we want your input! 💬

What features matter most? What’s your price ceiling?

Take our 2-min survey 👉 forms.gle/EMrSJQ6dmw4P...

🎁 One respondent will win a beautiful 150mm silicon wafer!

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Reposted by YosysHQ

ZenithVal @zenithval.com · Apr 10

Bad AAPL

190 4.1K 13K

Reposted by YosysHQ

Flux @willflux.bsky.social · Mar 24

Good news open-source #FPGA fans, there's a new release of nextpnr (place and route) from @yosyshq.com. The release notes mention "Numerous improvements to Gowin support": github.com/YosysHQ/next...

Release nextpnr 0.8 · YosysHQ/nextpnr

Remove nextpnr-gowin; replaced by Gowin support in nextpnr-himbaechel Remove unmaintained FPGA interchange support Updated and reworked CMake build system Himbaechel: Numerous improvements to Gowin...

github.com

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YosysHQ @yosyshq.com · Feb 20

Join us in a few hours for a talk about ASIC synthesis with Yosys!

18:00 CET / 22:30 IST / 09:00 PT

meet.jit.si/yosys-users-...

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YosysHQ @yosyshq.com · Feb 18

Emil will be covering:

* ASIC synthesis in general
* Yosys scripts
* abc scripts
* New Yosys features for ASIC

Join us at 18:00 CET / 22:30 IST / 09:00 PT on Thursday 20th.

Sign up to our mailing list to get a reminder before the event: blog.yosyshq.com/newsletter/

Newsletter

Sign up to our newsletter and don't miss a post!

blog.yosyshq.com

YosysHQ @yosyshq.com · Feb 18

It's time for another YUG! What's a YUG? It's the Yosys User's Group! For anyone interested in using Yosys - we've had sessions on primitives, plugins, hardware security, FPGAs and lots more...

This time we'll be turning to #ASIC synthesis with our own Emil Jiří Tywoniak.

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Reposted by YosysHQ

Matt Venn @mattvenn.net · Feb 3

Simulation is the #ASIC terminology of the week!
In the last month, Simulation has been the 35th most popular out of 42 terms.

Simulation

Simulation is the ASIC terminology of the week!

www.zerotoasiccourse.com

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YosysHQ @yosyshq.com · Feb 3

Looking for a tiny RISC-V core that scales with your needs?

We covered FazyRV by Meinhard Kissich in our community spotlight last year: blog.yosyshq.com/p/community-...

Now it's been silicon proven on @tinytapeout.com !

www.linkedin.com/posts/meinha...

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Reposted by YosysHQ

JauntyWunderKind @jauntywk.bsky.social · Jan 21

Insta-follow, nice! Looking forward to your dive in to interesting off the main path of @yosyshq.com bit.

Gonna have to figure out what other fpga/yosys/openfpga nerds there are to follow here that I'm missing!

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Reposted by YosysHQ

Flux @willflux.bsky.social · Jan 31

Fearlessly generate your own clocks with Lattice ECP5 #FPGAs and Yosys. Includes worked examples for #ULX3S and easy to adapt to any dev board. Happy #FPGAFriday! @yosyshq.com projectf.io/posts/ecp5-f...

ECP5 FPGA Clock Generation

Yosys and nextpnr have excellent support for Lattice ECP5 FPGAs. However, without using the ECP5 PLL (phase-locked loop), you’re stuck running at the speed of your dev board oscillator. This post outl...

projectf.io

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Reposted by YosysHQ

Flux @willflux.bsky.social · Jan 21

Working on a new #FPGA blog post this evening. I'll be sharing the draft with my sponsors in the next few days. @yosyshq.com

"Yosys and nextpnr have excellent support for Lattice ECP5 FPGAs. However, without using the ECP5 PLL, you're stuck running at the speed of your dev board oscillator..."

Yosys and nextpnr have excellent support for Lattice ECP5 FPGAs. However, without using the ECP5 PLL (phase-locked loop), you're stuck running at the speed of your dev board oscillator. This post outlines the frequency capabilities of the ECP5 PLL and provides several practical examples to get you started with generating custom clock frequencies.

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