... ask HISTORIANS???
August 20, 2025 at 11:39 AM
... ask HISTORIANS???
A brief history and (ab)use of __VA_OPT__: tavianator.com/2025/cpp_chu...
Taking the C preprocessor to Church - tavianator.com
tavianator.com
June 26, 2025 at 6:38 PM
A brief history and (ab)use of __VA_OPT__: tavianator.com/2025/cpp_chu...
Still no sound from my laptop speakers, but at least I won't trigger a UAF anymore while I try to debug it: lore.kernel.org/linux-sound/...
April 23, 2025 at 3:19 PM
Still no sound from my laptop speakers, but at least I won't trigger a UAF anymore while I try to debug it: lore.kernel.org/linux-sound/...
Reposted by Tavian Barnes
I could reproduce the phenomenon with only 14 instructions on #Intel #GoldenCove, #RaptorCove, #RedwoodCove. It appears only with the 64b-immediate initialization of the 2nd (3rd) operand in the -1024<=imm32<=1023 range.
On #LionCove... 1/2
On #LionCove... 1/2
January 8, 2025 at 6:32 PM
I could reproduce the phenomenon with only 14 instructions on #Intel #GoldenCove, #RaptorCove, #RedwoodCove. It appears only with the 64b-immediate initialization of the 2nd (3rd) operand in the -1024<=imm32<=1023 range.
On #LionCove... 1/2
On #LionCove... 1/2
New blog post: tavianator.com/2025/shlx.html
The Alder Lake SHLX anomaly - tavianator.com
tavianator.com
January 2, 2025 at 10:17 PM
New blog post: tavianator.com/2025/shlx.html
Reposted by Tavian Barnes
I wrote more details here: github.com/andreas-abel...
uops.info Alder Lake-P latency for SHLX · Issue #33 · andreas-abel/nanoBench
https://uops.info/html-instr/SHLX_R64_R64_R64.html#ADL-P lists SHLX as having 3-cycle latency for both operands. This is in contrast to Intel's docs and InstLatx64's measurements. So what gives? I ...
github.com
December 31, 2024 at 8:12 PM
I wrote more details here: github.com/andreas-abel...
So it turns out that on arm64 macOS, if you send SIGSEGV manually (kill -SEGV <pid>), the kernel fills in siginfo->si_code as if it were a "real" SIGSEGV. So your handler can't easily distinguish between a "real" and a "fake" SIGSEGV
December 22, 2024 at 7:25 PM
So it turns out that on arm64 macOS, if you send SIGSEGV manually (kill -SEGV <pid>), the kernel fills in siginfo->si_code as if it were a "real" SIGSEGV. So your handler can't easily distinguish between a "real" and a "fake" SIGSEGV
A while ago I implemented some code for dynamic signal handler (un)registration: github.com/tavianator/b...
The idea is you can call sighook(SIGINT, ...) from multiple places and all the registered hooks will get called when a signal is received.
The idea is you can call sighook(SIGINT, ...) from multiple places and all the registered hooks will get called when a signal is received.
github.com
December 17, 2024 at 5:38 PM
A while ago I implemented some code for dynamic signal handler (un)registration: github.com/tavianator/b...
The idea is you can call sighook(SIGINT, ...) from multiple places and all the registered hooks will get called when a signal is received.
The idea is you can call sighook(SIGINT, ...) from multiple places and all the registered hooks will get called when a signal is received.
Does anyone have a good writeup of the behaviour of explicit prefetches on modern x86 uarches? In particular the cost of prefetching an invalid address (unmapped or even non-canonical).
November 25, 2024 at 8:17 PM
Does anyone have a good writeup of the behaviour of explicit prefetches on modern x86 uarches? In particular the cost of prefetching an invalid address (unmapped or even non-canonical).
Made a quick script to compare `perf stat` results: gist.github.com/tavianator/b...
November 14, 2024 at 12:32 AM
Made a quick script to compare `perf stat` results: gist.github.com/tavianator/b...
Wrote up my experience finding (and fixing) a bug in Btrfs: tavianator.com/2024/btrfs_b...
Bug hunting in Btrfs - tavianator.com
tavianator.com
March 18, 2024 at 7:54 PM
Wrote up my experience finding (and fixing) a bug in Btrfs: tavianator.com/2024/btrfs_b...