@memblers.bsky.social
I put in a random 8 char code one time on SMB3, like 20 years ago, and got that extended 1-up jingle. Surprised the crap out my friend and I. Unfortunately didn't remember the code, really wasn't expecting any result from that.
June 7, 2025 at 8:52 AM
I put in a random 8 char code one time on SMB3, like 20 years ago, and got that extended 1-up jingle. Surprised the crap out my friend and I. Unfortunately didn't remember the code, really wasn't expecting any result from that.
cc65 is great, but I'd recommend llvm-mos or vbcc over it, these days. If performance matters.
April 22, 2025 at 9:33 AM
cc65 is great, but I'd recommend llvm-mos or vbcc over it, these days. If performance matters.
Mapper 7 games are mostly by Rare, and they often do insanely tricky stuff requiring cycle perfect PPU timing.
October 29, 2024 at 9:27 AM
Mapper 7 games are mostly by Rare, and they often do insanely tricky stuff requiring cycle perfect PPU timing.
Bigfoot hill climb event is another example.
October 28, 2024 at 1:51 PM
Bigfoot hill climb event is another example.
Right now I planned 8-bit wide mapper register, vs the MMC1-like serial one, that's my last resort to free up I/Os.
My thinking is that lots of WRAM makes it practical to hold pattern tiles as code, load immediate / sta $2007, so for 8x8 modes one can still get by with limited CHR bankswitching.
My thinking is that lots of WRAM makes it practical to hold pattern tiles as code, load immediate / sta $2007, so for 8x8 modes one can still get by with limited CHR bankswitching.
October 26, 2024 at 7:55 PM
Right now I planned 8-bit wide mapper register, vs the MMC1-like serial one, that's my last resort to free up I/Os.
My thinking is that lots of WRAM makes it practical to hold pattern tiles as code, load immediate / sta $2007, so for 8x8 modes one can still get by with limited CHR bankswitching.
My thinking is that lots of WRAM makes it practical to hold pattern tiles as code, load immediate / sta $2007, so for 8x8 modes one can still get by with limited CHR bankswitching.
You still have to populate all 32x30 entries, then it would fetch pattern data from 4 different banks for each metatile quadrant.
The only thing that worries me a bit is only having enough I/O for 32kB CHR RAM, hopefully that's not too limiting.
The only PPU inputs are PPU RD, A0, A5, it's crazy.
The only thing that worries me a bit is only having enough I/O for 32kB CHR RAM, hopefully that's not too limiting.
The only PPU inputs are PPU RD, A0, A5, it's crazy.
October 26, 2024 at 7:11 PM
You still have to populate all 32x30 entries, then it would fetch pattern data from 4 different banks for each metatile quadrant.
The only thing that worries me a bit is only having enough I/O for 32kB CHR RAM, hopefully that's not too limiting.
The only PPU inputs are PPU RD, A0, A5, it's crazy.
The only thing that worries me a bit is only having enough I/O for 32kB CHR RAM, hopefully that's not too limiting.
The only PPU inputs are PPU RD, A0, A5, it's crazy.