Pongsagon vichit
mattdiygraphics.bsky.social
Pongsagon vichit
@mattdiygraphics.bsky.social
Amateur FPGA designer
Spec:
- GPU can performs transformation & lighting, rasterization
- 4-bit double buffer, 8-bit z buffer store on QSPI RAM
- max tri 1K
- backface culling
- 1 directional light, flat shading
- use Gamepad to transform the model & light
- run at 25Mhz. When fab, it will use around 200k transistor
November 3, 2025 at 6:17 AM
Great! Thanks
October 22, 2025 at 2:12 AM
Just got the Pmod today. To use QSPI Pmod that was plugged into Audio Pmod, do I have to cut the trace of RAM B?(sacrifice RAM B to make room for audio)

Thanks for your work. 👍
October 21, 2025 at 10:33 AM
Nice one. Glad that someone finally do RP2350 with DVI. I have wait for Adafruit to do it but it seem that they dont do it this time. I really like their Feather RP2040 DVI. I bought them a lot to do keychain size 2D/3D game console projects.
June 11, 2025 at 2:07 AM
I see. At first, I think you are using a QSPI pmod with two RAM. I am using your QSPI pmod on my next TinyTapeout project. Trying to study your qspi controller code. Thanks a lot for sharing it.
June 10, 2025 at 1:33 AM
When do you write new pixels to the buffer on PSRAM? From my understanding, you use all the RAM bandwidth in the non-blanking interval. Is blanking interval enough to write all the pixels? Thanks.
June 9, 2025 at 12:54 PM
Thank you again for your answer. It seems more complicated than I though. Since, I have almost zero knowledge in DDR now. I cannot extraploate all the RAM issues that you are planning to manage. I will surely going to come back to read this again. 🙏
April 3, 2025 at 5:34 AM
This post is a gem, valuable experiment. How do you plan to do time sharing of your RAM with the framebuffer, texture and geometry data?
April 2, 2025 at 5:06 PM
Not sure I understand it. I have not try DRAM yet. So the bottleneck is the RAM bandwidth right? You are using 16 rasterizers (that can output 16 pixels at a time) because they would reach the peak bandwidth of your DRAM spec. No reason to do more than 16 rasterizers.
April 2, 2025 at 4:53 PM
Ok, so the no framebuffer version, your strategy is to max out BRAM to buy more time for beam race right? Instead of using just double line buffers. Nice.
April 2, 2025 at 4:24 PM
Wow, thanks a lot for your detailed answer. Please allow me to buy you a cup of coffee for this haha. You really are the Taylor Swift of FPGA. Never disappoint his fan.
April 2, 2025 at 4:14 PM
PS. I just received my Tinytapeout Tiniest ASIC GPU back. It work 😁. github.com/pongsagon/tt.... Your comment on my design would be invaluable to me. Thanks.
GitHub - pongsagon/tt07-tiniest-gpu: A tiniest GPU that can render only two texture mapped triangles
A tiniest GPU that can render only two texture mapped triangles - GitHub - pongsagon/tt07-tiniest-gpu: A tiniest GPU that can render only two texture mapped triangles
github.com
April 1, 2025 at 6:01 AM
Thanks for the blog. Two questions sir.
1. When writing pixels from 16 rasterizers, do you write to the same framebuffer or do you have 16 little framebuffers that stitched into one.
2. if 16 rasterizers need texture data, how do you plan to distribute the data.
Many thanks
April 1, 2025 at 5:54 AM
Thanks. Hard to find tutorial on AXI and SoC.
December 22, 2024 at 12:53 AM
Happy to see you post again. Looking forward to it.
December 18, 2024 at 9:08 AM