V9958 precharges the bus for half of each pixel cycle.

ASIC design manuals from the 80-90s recommended adding 1 or 0-tied driving buffers to prevent floating nodes when a bus is empty, but I never saw any arcade game manufacturer deal with that.

Only the test register does not use an R/W strobe. All other areas, including the VRC and wavetable, explicitly use the strobe. Maybe a mistake?

When performing four consecutive reads from the address range assigned as the test register, if a specific string is read, IKASCC can be easily determined. Actual chips will output a certain pattern that differs for each chip.

I checked all input/output transistors involved in the internal data bus, and found no pull-up/pull-down resistors. I've seen the internal tri-state bus four times, and all four chips left the bus in a floating state when not in use.

At this time, the internal tri-state bus is Hi-Z, so invalid(garbage) data on the bus become an input of the test register. FPGAs lack internal tri buses, and to ease integration, data input/output buses must be separated. Therefore, I modified the test register to write only during the write cycle.

The SCC test register was found to store bus input data into the test register during either read or write cycles(!!)

Reading the SCC test register activates the chip data bus driver's output, and the data bus input accepts the output data as-is.

I'll let you know the results after a deep check.

I'll let you know if there are any updates.

Ah, well then, this is quite important information. I'll check the read strobe for Ch.3 only. As far as I recall, Ch.1 through 3 were just repetitions of the same hardware. And the read strobe wasn't touched any further afaik. I'll double-check it again. Thank you.

the data occupying the bus immediately before the read cycle, temperature, and voltage. Each silicon exhibits its own tendency. I believe you have observed this phenomenon.

When reading the test register, all drivers on the internal tri-state bus are turned off. In this case, the value on the tri-state bus is not valid. The value read at this time varies depending on the characteristics of the specific silicon,

Reading the write only test register does not affect the register data in any way. The test register contents are 0 immediately after reset. If only D6 is 1, ch5 will sample data from the CPU data bus and produce garbage sound. Did you verify the actual chip's behavior without using an MSX?

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