I was scaling rdtsc cycles by boost/base clocks but instead dividing by integer add latency (.4;1.4 cycles on zen 5;5c) results in the same performance on both cores. Thanks for the information!

I ran some experiments for AVX-512 VFMADD PS/PD on Strix Point and I'm seeing 4;8 cycle latency and 1;.5 inst/cycle on Zen 5;5c. This aligns with what I've read on STX using 256-bit data paths, but looks like some delta between 5 and 5c

Any note of the device used for eval? I'm curious if 5 and 5c differ at all

Are they computing % of peak for M2 throughput according to M4 peak throughput? I'd expect M2 peak to be double and efficiency be worse, not better

It might run longer but there's no way to be sure

Have you tried jal 0