arXiv cs.AR Hardware Architecture
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Reposted by arXiv cs.AR Hardware Architecture
Bugra Kilictas, Faruk Alpay: Bare-Metal Tensor Virtualization: Overcoming the Memory Wall in Edge-AI Inference on ARM64 https://arxiv.org/abs/2601.03324 https://arxiv.org/pdf/2601.03324 https://arxiv.org/html/2601.03324
January 8, 2026 at 6:30 AM
Bugra Kilictas, Faruk Alpay: Bare-Metal Tensor Virtualization: Overcoming the Memory Wall in Edge-AI Inference on ARM64 https://arxiv.org/abs/2601.03324 https://arxiv.org/pdf/2601.03324 https://arxiv.org/html/2601.03324
[2026-01-08 Thu (UTC), no new articles found for csAR Hardware Architecture]
January 8, 2026 at 6:29 AM
[2026-01-08 Thu (UTC), no new articles found for csAR Hardware Architecture]
Reposted by arXiv cs.AR Hardware Architecture
Tianqi Zhang, Flavio Ponzina, Tajana Rosing: SpANNS: Optimizing Approximate Nearest Neighbor Search for Sparse Vectors Using Near Memory Processing https://arxiv.org/abs/2601.03229 https://arxiv.org/pdf/2601.03229 https://arxiv.org/html/2601.03229
January 7, 2026 at 6:30 AM
Tianqi Zhang, Flavio Ponzina, Tajana Rosing: SpANNS: Optimizing Approximate Nearest Neighbor Search for Sparse Vectors Using Near Memory Processing https://arxiv.org/abs/2601.03229 https://arxiv.org/pdf/2601.03229 https://arxiv.org/html/2601.03229
Reposted by arXiv cs.AR Hardware Architecture
Md. Anowar Hossain, Mohd. Ehsanul Hoque: Advancing Assistive Robotics: Multi-Modal Navigation and Biophysical Monitoring for Next-Generation Wheelchairs https://arxiv.org/abs/2601.02766 https://arxiv.org/pdf/2601.02766 https://arxiv.org/html/2601.02766
January 7, 2026 at 6:34 AM
Md. Anowar Hossain, Mohd. Ehsanul Hoque: Advancing Assistive Robotics: Multi-Modal Navigation and Biophysical Monitoring for Next-Generation Wheelchairs https://arxiv.org/abs/2601.02766 https://arxiv.org/pdf/2601.02766 https://arxiv.org/html/2601.02766
Kuilian Yang, Li Zhang, Ahmed M. Eltawil, Khaled Nabil Salama: Sparsity-Aware Streaming SNN Accelerator with Output-Channel Dataflow for Automatic Modulation Classification https://arxiv.org/abs/2601.02613 https://arxiv.org/pdf/2601.02613 https://arxiv.org/html/2601.02613
January 7, 2026 at 6:29 AM
Kuilian Yang, Li Zhang, Ahmed M. Eltawil, Khaled Nabil Salama: Sparsity-Aware Streaming SNN Accelerator with Output-Channel Dataflow for Automatic Modulation Classification https://arxiv.org/abs/2601.02613 https://arxiv.org/pdf/2601.02613 https://arxiv.org/html/2601.02613
[2026-01-07 Wed (UTC), 1 new article found for csAR Hardware Architecture]
January 7, 2026 at 6:29 AM
[2026-01-07 Wed (UTC), 1 new article found for csAR Hardware Architecture]
Reposted by arXiv cs.AR Hardware Architecture
Emrah Mete, Emin Erkan Korkmaz: Neuro-Channel Networks: A Multiplication-Free Architecture by Biological Signal Transmission https://arxiv.org/abs/2601.02253 https://arxiv.org/pdf/2601.02253 https://arxiv.org/html/2601.02253
January 6, 2026 at 6:35 AM
Emrah Mete, Emin Erkan Korkmaz: Neuro-Channel Networks: A Multiplication-Free Architecture by Biological Signal Transmission https://arxiv.org/abs/2601.02253 https://arxiv.org/pdf/2601.02253 https://arxiv.org/html/2601.02253
Reposted by arXiv cs.AR Hardware Architecture
Jorge L. Ruiz Williams: Warp-Cortex: An Asynchronous, Memory-Efficient Architecture for Million-Agent Cognitive Scaling on Consumer Hardware https://arxiv.org/abs/2601.01298 https://arxiv.org/pdf/2601.01298 https://arxiv.org/html/2601.01298
January 6, 2026 at 6:33 AM
Jorge L. Ruiz Williams: Warp-Cortex: An Asynchronous, Memory-Efficient Architecture for Million-Agent Cognitive Scaling on Consumer Hardware https://arxiv.org/abs/2601.01298 https://arxiv.org/pdf/2601.01298 https://arxiv.org/html/2601.01298
Liu Shijie, Zeng Zhenghao, Jiao Han, Huang Yihua: HFRWKV: A High-Performance Fully On-Chip Hardware Accelerator for RWKV https://arxiv.org/abs/2601.02135 https://arxiv.org/pdf/2601.02135 https://arxiv.org/html/2601.02135
January 6, 2026 at 6:29 AM
Liu Shijie, Zeng Zhenghao, Jiao Han, Huang Yihua: HFRWKV: A High-Performance Fully On-Chip Hardware Accelerator for RWKV https://arxiv.org/abs/2601.02135 https://arxiv.org/pdf/2601.02135 https://arxiv.org/html/2601.02135
Leandro Lanzieri, Jiri Kral, Goerschwin Fey, Holger Schlarb, Thomas C. Schmidt: Ageing Monitoring for Commercial Microcontrollers Based on Timing Windows https://arxiv.org/abs/2601.02053 https://arxiv.org/pdf/2601.02053 https://arxiv.org/html/2601.02053
January 6, 2026 at 6:29 AM
Leandro Lanzieri, Jiri Kral, Goerschwin Fey, Holger Schlarb, Thomas C. Schmidt: Ageing Monitoring for Commercial Microcontrollers Based on Timing Windows https://arxiv.org/abs/2601.02053 https://arxiv.org/pdf/2601.02053 https://arxiv.org/html/2601.02053
Nick Lindsay, Caroline Trippel, Anurag Khandelwal, Abhishek Bhattacharjee: CounterPoint: Using Hardware Event Counters to Refute and Refine Microarchitectural Assumptions (Extended Version) https://arxiv.org/abs/2601.01265 https://arxiv.org/pdf/2601.01265 https://arxiv.org/html/2601.01265
January 6, 2026 at 6:29 AM
Nick Lindsay, Caroline Trippel, Anurag Khandelwal, Abhishek Bhattacharjee: CounterPoint: Using Hardware Event Counters to Refute and Refine Microarchitectural Assumptions (Extended Version) https://arxiv.org/abs/2601.01265 https://arxiv.org/pdf/2601.01265 https://arxiv.org/html/2601.01265
Yilun Zhao, Yu Chen, Kaiyan Chang, He Li, Bing Li, Yinhe Han, Ying Wang: A System Architecture for Low Latency Multiprogramming Quantum Computing https://arxiv.org/abs/2601.01158 https://arxiv.org/pdf/2601.01158 https://arxiv.org/html/2601.01158
January 6, 2026 at 6:29 AM
Yilun Zhao, Yu Chen, Kaiyan Chang, He Li, Bing Li, Yinhe Han, Ying Wang: A System Architecture for Low Latency Multiprogramming Quantum Computing https://arxiv.org/abs/2601.01158 https://arxiv.org/pdf/2601.01158 https://arxiv.org/html/2601.01158
[2026-01-06 Tue (UTC), 4 new articles found for csAR Hardware Architecture]
January 6, 2026 at 6:29 AM
[2026-01-06 Tue (UTC), 4 new articles found for csAR Hardware Architecture]
Reposted by arXiv cs.AR Hardware Architecture
Yasaman Khorsandmanesh, Emil Bjornson, Joakim Jalden: Splitting Precoding with Subspace Selection and Quantized Refinement for Massive MIMO https://arxiv.org/abs/2601.00616 https://arxiv.org/pdf/2601.00616 https://arxiv.org/html/2601.00616
January 5, 2026 at 6:36 AM
Yasaman Khorsandmanesh, Emil Bjornson, Joakim Jalden: Splitting Precoding with Subspace Selection and Quantized Refinement for Massive MIMO https://arxiv.org/abs/2601.00616 https://arxiv.org/pdf/2601.00616 https://arxiv.org/html/2601.00616
Reposted by arXiv cs.AR Hardware Architecture
Hongjian Zhou, Ziang Yin, Jiaqi Gu: Democratizing Electronic-Photonic AI Systems: An Open-Source AI-Infused Cross-Layer Co-Design and Design Automation Toolflow https://arxiv.org/abs/2601.00130 https://arxiv.org/pdf/2601.00130 https://arxiv.org/html/2601.00130
January 5, 2026 at 6:48 AM
Hongjian Zhou, Ziang Yin, Jiaqi Gu: Democratizing Electronic-Photonic AI Systems: An Open-Source AI-Infused Cross-Layer Co-Design and Design Automation Toolflow https://arxiv.org/abs/2601.00130 https://arxiv.org/pdf/2601.00130 https://arxiv.org/html/2601.00130
Reposted by arXiv cs.AR Hardware Architecture
Yin, Zhou, Gangi, Zhang, Zhang, Huang, Gu: Toward Large-Scale Photonics-Empowered AI Systems: From Physical Design Automation to System-Algorithm Co-Exploration https://arxiv.org/abs/2601.00129 https://arxiv.org/pdf/2601.00129 https://arxiv.org/html/2601.00129
January 5, 2026 at 6:48 AM
Yin, Zhou, Gangi, Zhang, Zhang, Huang, Gu: Toward Large-Scale Photonics-Empowered AI Systems: From Physical Design Automation to System-Algorithm Co-Exploration https://arxiv.org/abs/2601.00129 https://arxiv.org/pdf/2601.00129 https://arxiv.org/html/2601.00129
Elham Cheshmikhani, Hamed Farbeh, Hossein Asadi: ROBIN: Incremental Oblique Interleaved ECC for Reliability Improvement in STT-MRAM Caches https://arxiv.org/abs/2601.00456 https://arxiv.org/pdf/2601.00456 https://arxiv.org/html/2601.00456
January 5, 2026 at 6:29 AM
Elham Cheshmikhani, Hamed Farbeh, Hossein Asadi: ROBIN: Incremental Oblique Interleaved ECC for Reliability Improvement in STT-MRAM Caches https://arxiv.org/abs/2601.00456 https://arxiv.org/pdf/2601.00456 https://arxiv.org/html/2601.00456
Elham Cheshmikhani, Hamed Farbeh, Hossein Asadi: Enhancing Reliability of STT-MRAM Caches by Eliminating Read Disturbance Accumulation https://arxiv.org/abs/2601.00450 https://arxiv.org/pdf/2601.00450 https://arxiv.org/html/2601.00450
January 5, 2026 at 6:29 AM
Elham Cheshmikhani, Hamed Farbeh, Hossein Asadi: Enhancing Reliability of STT-MRAM Caches by Eliminating Read Disturbance Accumulation https://arxiv.org/abs/2601.00450 https://arxiv.org/pdf/2601.00450 https://arxiv.org/html/2601.00450
[2026-01-05 Mon (UTC), 2 new articles found for csAR Hardware Architecture]
January 5, 2026 at 6:29 AM
[2026-01-05 Mon (UTC), 2 new articles found for csAR Hardware Architecture]
[2026-01-02 Fri (UTC), no new articles found for csAR Hardware Architecture]
January 2, 2026 at 6:34 AM
[2026-01-02 Fri (UTC), no new articles found for csAR Hardware Architecture]
Reposted by arXiv cs.AR Hardware Architecture
Sergio Alvarez-Telena, Marta Diez-Fernandez: Advances in Agentic AI: Back to the Future https://arxiv.org/abs/2512.24856 https://arxiv.org/pdf/2512.24856 https://arxiv.org/html/2512.24856
January 1, 2026 at 6:35 AM
Sergio Alvarez-Telena, Marta Diez-Fernandez: Advances in Agentic AI: Back to the Future https://arxiv.org/abs/2512.24856 https://arxiv.org/pdf/2512.24856 https://arxiv.org/html/2512.24856
Reposted by arXiv cs.AR Hardware Architecture
Fen-Yu Hsieh, Yun-Chang Teng, Ding-Yong Hong, Jan-Jan Wu: FPGA Co-Design for Efficient N:M Sparse and Quantized Model Inference https://arxiv.org/abs/2512.24713 https://arxiv.org/pdf/2512.24713 https://arxiv.org/html/2512.24713
January 1, 2026 at 6:33 AM
Fen-Yu Hsieh, Yun-Chang Teng, Ding-Yong Hong, Jan-Jan Wu: FPGA Co-Design for Efficient N:M Sparse and Quantized Model Inference https://arxiv.org/abs/2512.24713 https://arxiv.org/pdf/2512.24713 https://arxiv.org/html/2512.24713
Reposted by arXiv cs.AR Hardware Architecture
Bin Xu, Ayan Banerjee, Sandeep Gupta: Enabling Physical AI at the Edge: Hardware-Accelerated Recovery of System Dynamics https://arxiv.org/abs/2512.23767 https://arxiv.org/pdf/2512.23767 https://arxiv.org/html/2512.23767
January 1, 2026 at 6:32 AM
Bin Xu, Ayan Banerjee, Sandeep Gupta: Enabling Physical AI at the Edge: Hardware-Accelerated Recovery of System Dynamics https://arxiv.org/abs/2512.23767 https://arxiv.org/pdf/2512.23767 https://arxiv.org/html/2512.23767
Yaoyun Zhou, Qian Wang: HERO-Sign: Hierarchical Tuning and Efficient Compiler-Time GPU Optimizations for SPHINCS+ Signature Generation https://arxiv.org/abs/2512.23969 https://arxiv.org/pdf/2512.23969 https://arxiv.org/html/2512.23969
January 1, 2026 at 6:29 AM
Yaoyun Zhou, Qian Wang: HERO-Sign: Hierarchical Tuning and Efficient Compiler-Time GPU Optimizations for SPHINCS+ Signature Generation https://arxiv.org/abs/2512.23969 https://arxiv.org/pdf/2512.23969 https://arxiv.org/html/2512.23969
[2026-01-01 Thu (UTC), 1 new article found for csAR Hardware Architecture]
January 1, 2026 at 6:29 AM
[2026-01-01 Thu (UTC), 1 new article found for csAR Hardware Architecture]