Claire Xen 🏳️‍⚧️ 🧙🏻‍♀️ 💖💛💙
clairexen.bsky.social
Claire Xen 🏳️‍⚧️ 🧙🏻‍♀️ 💖💛💙
@clairexen.bsky.social
Neurodiverse Trans Geek Girl 🧙‍♀️
Queer Kinky Poly Mess 🏳️‍🌈 🏳️‍⚧️
CTO @YosysHQ 😺 RISC-V, SMT 👩‍💻
Opinions are my Ceti eel's 😛
ACAB BLM ✊ I am Antifa 🏴🚩
Vienna, Austria 📌 she/her 🧚‍♀️
Reposted by Claire Xen 🏳️‍⚧️ 🧙🏻‍♀️ 💖💛💙
Congratulations @clairexen.bsky.social: #HotChips / IEEE TCMM 2025 Open Source Hardware Contribution Award
August 27, 2025 at 1:33 AM
Reposted by Claire Xen 🏳️‍⚧️ 🧙🏻‍♀️ 💖💛💙
So if you are currently involved with ISA-level decisions about inclusion of any pext/pdep-like instructions:

Please consider including SAG/inverse-SAG with bit-reversal of the goats.

No matter which of the two implementation methods you are using: All you need to do is not mask the goat bits.
July 25, 2025 at 11:30 PM
Reposted by Claire Xen 🏳️‍⚧️ 🧙🏻‍♀️ 💖💛💙
Here is the code:
github.com/clairexen/ed...

I can't see any obvious reason why that identity should not extend beyond 8-bit units. But I have not actually tested that hypothesis yet.
July 24, 2025 at 12:38 PM
Reposted by Claire Xen 🏳️‍⚧️ 🧙🏻‍♀️ 💖💛💙
I have to make a correction regarding ☝️. I've now implemented the Hilewitz-Lee method as well in my edu-sag repository. And it implements the bit-reflecting-SAG as-is. All you have to do is to remove the '&ci' from the data input, thus it's always more area to implement PEXT than bit-reflecting-SAG.
July 24, 2025 at 12:38 PM
Reposted by Claire Xen 🏳️‍⚧️ 🧙🏻‍♀️ 💖💛💙
I wrote a reference implementation for a SAG without bit reflection: github.com/clairexen/ed..., and I wrote a parametric SAG core for any bit width: github.com/clairexen/ed...
edu-sag/param.v at main · clairexen/edu-sag
Educational 8-Bit Sheep-And-Goats (SAG) Verilog Reference IP - clairexen/edu-sag
github.com
June 20, 2025 at 4:04 PM
To have trans friends is to hold candles in the wind.

I can’t say if the storm is fate or man-made.

I only know I’m losing light.
June 9, 2025 at 8:32 PM
Reposted by Claire Xen 🏳️‍⚧️ 🧙🏻‍♀️ 💖💛💙
Yes, I mean the definition of SAG with the mirroring. The non-mirrored version is way more expensive (and IMO actually less desirable anyway).

I just wrote this:
github.com/clairexen/ed...

I've been meaning to write this code for quite some time...
GitHub - clairexen/edu-sag: Educational 8-Bit Sheep-And-Goats (SAG) Verilog Reference IP
Educational 8-Bit Sheep-And-Goats (SAG) Verilog Reference IP - clairexen/edu-sag
github.com
June 6, 2025 at 9:27 AM
Long time no see, Metalab Vienna
March 5, 2025 at 9:14 PM
When I was little I wanted a time machine. Now I have (c)PTSD. Beware what you wish for.
January 16, 2025 at 9:32 AM
I've just posted a reminder on Twitter, that I am now on bsky. Let's make this a doubly linked list: Just in case you wanna see my old Twitter, that I'm not using anymore, here you go: twitter.com/oe1cxw (it'll forward you to "X" but hell no I won't post an X link for this, or call it my "old X" :P)
January 13, 2025 at 3:53 PM
Reposted by Claire Xen 🏳️‍⚧️ 🧙🏻‍♀️ 💖💛💙
... and it has a robust CSG engine,
described in arxiv.org/abs/2405.12949 (that just got accepted pending minor revisions)
November 26, 2024 at 4:11 PM
Reposted by Claire Xen 🏳️‍⚧️ 🧙🏻‍♀️ 💖💛💙
Introducing the Zero to ASIC analog course!

youtu.be/wM4cobfjMMQ

Don't miss the Black Friday discounts - join the newsletter for $150 off on Friday: zerotoasiccourse.com/newsletter/

Full course details: zerotoasiccourse.com/analog/
Introducing the Zero to ASIC analog course!
YouTube video by Zero To ASIC Course
youtu.be
November 25, 2024 at 5:28 PM
Reposted by Claire Xen 🏳️‍⚧️ 🧙🏻‍♀️ 💖💛💙
After a summer break, our user group meetings have resumed again!

In our last call, Katharina CeesaySeitz from ETH Zürich presented her work to detect microarchitectural information leakage via hardware timing side channels.

Watch her talk on our Youtube channel!

www.youtube.com/watch?v=Kxp-...
yug8
YouTube video by YosysHQ
www.youtube.com
November 26, 2024 at 11:31 AM
Thread for #wordle

Wordle 1,255 2/6*

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November 25, 2024 at 3:18 PM
Reposted by Claire Xen 🏳️‍⚧️ 🧙🏻‍♀️ 💖💛💙
1st post on bluesky!
November 18, 2024 at 4:19 PM
Reposted by Claire Xen 🏳️‍⚧️ 🧙🏻‍♀️ 💖💛💙
I've updated my "rules for ready/valid handshakes" to describe both a control implementation I made heavy use of in the past year, and to add discussion on the synchronization operation which underlies ready/valid handshakes, much like ready/valid handshakes underlie AXI4.
fpgacpu.ca/fpga/handsha...
Rules for Ready/Valid Handshakes
A set of rules for consistent and high-performance designs with ready/valid handshakes, and a discussion of the underlying synchronization mechanism.
fpgacpu.ca
May 31, 2024 at 1:06 PM
Wordle 1,082 3/6*

⬜🟨🟨⬜⬜
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ROFL 🤣
June 5, 2024 at 4:07 AM
Wordle 900 2/6*

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December 6, 2023 at 12:10 AM
I probably spent way too much time fiddling with those functions today.. But I'm quite happy with what I ended up with. ツ
November 5, 2023 at 4:40 AM
Wow. ChatGPT knows about my transition and my new name, but only if you know about it as well.
October 27, 2023 at 8:52 PM
When I was working on RISC-V BitManip I was doing inverse xorshift as a benchmark example.

This picture makes a lot of sense ;)
October 24, 2023 at 9:51 AM
Reposted by Claire Xen 🏳️‍⚧️ 🧙🏻‍♀️ 💖💛💙
different fields of math are a scam to sell more wikipedia articles.

it's all the same math, just rearranged
October 19, 2023 at 5:37 AM
Gotta post something here as well I guess.. 😅 so here are some selfies I found on my phone that I kinda like 🦋💜✨ #firstpost
October 24, 2023 at 4:30 AM