Author | Lightnews

InstLatX64 @instlatx64.bsky.social · 5d

Sources:
[1]: lore.kernel.org/all/17617415...
[2]: docs.amd.com/v/u/en-US/58...
[3]: deic.dk/sites/defaul...
[4]: www.phoronix.com/image-viewer...
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InstLatX64 @instlatx64.bsky.social · 5d

#AMD CPUID refresh:
-- CPUID B80F00 is #Zen6 [1]
-- #Zen5c #Sorano CPUID is B10F00 (#EPYC 8005, SP6 socket) [2],[3]
-- #Zen5 #Grado CPUID is B40F40 (EPYC 4005, AM5 socket) [4]
GitHub:
github.com/InstLatx64/I...
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InstLatX64 @instlatx64.bsky.social · 6d

#Intel released the 89th edition of the Software Developer’s Manuals with a new SEAM, and completely rewritten CPUID (with domain info) section:
All-in-One:
cdrdv2-public.intel.com/868137/32546...
Changes v81:
cdrdv2-public.intel.com/868136/25204...
UDB (opcode D6h) canonized

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InstLatX64 @instlatx64.bsky.social · 7d

Not a clear commitment, but a very good sign: #APX appeared in Mark Papermaster's presentation
#OCP2025 #AMD #x86EAG
www.amd.com/en/blogs/202...
youtu.be/Z36PjXFBmig?...

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InstLatX64 @instlatx64.bsky.social · 8d

Unfortunately, #Intel does not answer openly Game.Keeps.Loading 's question regarding #NovaLake ISA:
community.intel.com/t5/Mobile-and-Desktop-Processors/Intel-APX-ACX-10-2/m-p/1723564#M86387

#APX #AVX10_1 #AVX10_2 #AVX512

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InstLatX64 @instlatx64.bsky.social · 12d

This contradicts the earlier info:
- homogenized, 512b-only #AVX10
- oneDNN 3.9 release note [1]
- 2:1 #PantherCove : #ArcticWolf die size
and the common sense, without #APX -capable desktop SKUs, APX will be rare on servers too...
[1]: bsky.app/profile/inst...

Phoronix @phoronix-poster.bsky.social · 13d

Intel Nova Lake Support Merged For GCC 16 Compiler - https://www.phoronix.com/news/Intel-Nova-Lake-GCC-16

Intel Nova Lake Support Merged For GCC 16 Compiler

Following last week LLVM/Clang 22 adding Intel Nova Lake with "-march=novalake" support, the GNU Compiler Collection (GCC) has now received similar treatment for the promising next-generation desktop processors...

www.phoronix.com

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InstLatX64 @instlatx64.bsky.social · 12d

#Intel #VPMM is back in the 7th edition of "Intel® TDX Module Base Architecture Specification (What Changed)".
Probably just a documentation bug.
cdrdv2-public.intel.com/867556/intel...

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InstLatX64 @instlatx64.bsky.social · 18d

#Intel #PantherLake presentation:
www.intel.com/content/www/...
#CougarCove #Darkmont #Intel18A

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InstLatX64 @instlatx64.bsky.social · 20d

#APX is also on the list
#ACE = #AMX

x.com/ravigiri/sta...

Ravi A Giri on X: "@InstLatX64 @FelixCLC_ @LeslieB82382206 @philparkbot Update on the progress of the x86 advisory group from the @AMD keynote by Mark Papermaster at #OCP2025 - AMX becomes ACE? https://t.co/ty1oZmwN8n" / X

@InstLatX64 @FelixCLC_ @LeslieB82382206 @philparkbot Update on the progress of the x86 advisory group from the @AMD keynote by Mark Papermaster at #OCP2025 - AMX becomes ACE? https://t.co/ty1oZmwN8n

x.com

InstLatX64 @instlatx64.bsky.social · 21d

perhaps #VPMM ~= ACE...
bsky.app/profile/inst...

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InstLatX64 @instlatx64.bsky.social · 21d

cc: @fclc.bsky.social

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InstLatX64 @instlatx64.bsky.social · 21d

#AMD & #Intel unified future instructions:
#FRED #AVX10 #ChkTag #ACE (=ACE (Advanced Matrix Extensions for Matrix Multiplication): www.amd.com/en/blogs/202...

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InstLatX64 @instlatx64.bsky.social · 21d

What happened to the SiSoftware Sandra? Why hasn't a new one been released since October 2023?
www.sisoftware.co.uk

SiSoftware – Windows, Android, GPGPU, CUDA, OpenCL, analysers, diagnostic and benchmarking apps

www.sisoftware.co.uk

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InstLatX64 @instlatx64.bsky.social · 24d

The Netwide Assembler 3.01 is ready and supports the full #DiamondRapids and #NovaLake instruction sets:
nasm.us
#AVX10_2 #AVX10_VNNI_INT #APX #AMX_FP8 #AMX_TF32 #AMX_COMPLEX #AMX_AVX512 #AMX_MOVRS

InstLatX64 @instlatx64.bsky.social · 24d

#Intel #ClearwaterForest #Xeon6+ presentation:
cdrdv2-public.intel.com/866623/xeon-...
#Darkmont #Intel18A #LGA7529

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InstLatX64 @instlatx64.bsky.social · 25d

New #AMD CPUID dump:
64-Core #ThreadripperPro 9985WX ( #ShimadaPeak, #Zen5) B00F81
GitHub:
github.com/InstLatx64/I...

InstLatX64 @instlatx64.bsky.social · 26d

It is a top-secret place :)

3

InstLatX64 @instlatx64.bsky.social · 27d

#AMD refreshed the "Revision Guide for AMD Family 1Ah Models 00h-0Fh Processors" 58251 to v1.10 pdf
(#Turin #Zen5 C1 CPUID B00F21 #EPYC)
docs.amd.com/v/u/en-US/58...

InstLatX64 @instlatx64.bsky.social · 27d

#AMD refreshed the "Revision Guide for AMD Family 1Ah Models 10h-1Fh Processors" 58730 to v1.30 pdf
(#TurinD #Zen5c B0 CPUID B10F10 #EPYC)
docs.amd.com/v/u/en-US/58...

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InstLatX64 @instlatx64.bsky.social · 27d

Thx!
#Intel Presler F62 Instlatx64 dump:
github.com/InstLatx64/I...

github.com

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InstLatX64 @instlatx64.bsky.social · 27d

Sources:
[1]:ISAExt Guide
cdrdv2-public.intel.com/865891/31943...
[2]:perfmon
github.com/intel/perfmo...
[3]:HotChips2025
www.servethehome.com/wp-content/u...

cdrdv2-public.intel.com

InstLatX64 @instlatx64.bsky.social · 28d

#Intel #Pantherlake #CougarCove/#Darkmont differences over the 18A process, so far:
- ISA additions (CGC/DMR)
- Better frontend/branch prediction (CGC/DMR)
- P21 bounded insts (CLMUL, GF2MUL?) doubled throughput (DMT)
- 19 -> 17 clks L2 latency (SMT->DMT)